FIGS. 21a and 21b show the structure and the principle of a tunnel magneto-resistive element, referred to below as TMR. Referring to FIG. 21a, a TMR 610 includes an insulating film 652 and magnetic layers 653, 654 formed on both sides thereof. The insulating film 652 has a thickness of 10 to 20 Å, while that of each of the magnetic layers 653, 654 is on the order of 50 Å. One 653 of the two magnetic layers 653, 654 is termed a pin layer having its direction of magnetization not changed by the application of the magnetic field within the operating range of the TMR but fixed to the direction of magnetization as set at the time of manufacture. The other magnetic layer 654, termed a free layer, has its direction of magnetization changed by the application of the magnetic field within the operating range of the TMR. FIG. 21a shows the state in which the free layer 654 is magnetized in a direction opposite to that of the pin layer 653. When an electric field is applied across the free layer 654 and the pin layer 653, the tunnel current flowing through the insulating film 652 is small, with the TMR exhibiting a high resistance value. If, in this state, a magnetic field, not less than a threshold value for inversion of magnetization of the free layer 654, is applied to the TMR 610 in a direction parallel to the direction of magnetization of the pin layer 653, the magnetization of the free layer 654 is reversed. FIG. 21b shows the state of the inversion of magnetization. If an electrical field is applied across the free layer 654 and the pin layer 653, the tunnel current flowing in the insulating film 652 becomes larger, with the resistance value of the TMR 610 being then decreased.
Such a semiconductor storage device, referred to below as MRAM, is known, in which the above-described resistance change of TMR is utilized such that the two resistance states of the TMR, for example, the high resistance state of FIG. 21a and the low resistance state of FIG. 21b are allocated to storage states of ‘1’ and ‘0’, respectively. FIGS. 22a and 22b are a plan view and a cross-sectional view for illustrating the operation of the MRAM memory cell, respectively. Referring to FIG. 22a, a word line 711 and a bit line 712 are arranged at right angles to each other on both sides, more precisely, on upper and lower sides, of the TMR 710. The directions indicated by solid-line arrows indicate the current-flowing directions. Referring to FIG. 22b, a TMR 710 is made up by an insulating film 752, a pin layer 753 and a free layer 754 on both sides of the insulating film 752, an anti-ferromagnetic layer 755, formed below the pin layer 753, and a cap layer 756. The anti-ferromagnetic layer 755 is provided for fixing the direction of magnetization of the pin layer 753 and for assuring facilitated inversion of only the direction of magnetization of the free layer 754. Consequently, the TMR 710 has a spin-valve structure. The cap layer 756 protects the anti-ferromagnetic layer 755 and the free layer 754. Data writing, that is, inversion of the direction of magnetization of the free layer 754, occurs by causing the current to flow through the word line 711 and the bit line 712. By the law of Ampere, when the current is flowing through the word line 711 and the bit line 712, in the direction shown in FIG. 22a, a magnetic field is generated in the free layer 754 from the lower side of the drawing sheet towards above in FIG. 22a, by the current flowing through the word line 711, whilst another magnetic field is generated in the free layer 754 from the left side towards the right side of the drawing sheet in FIG. 22a, by the current flowing through the bit line 712. Hence, a synthesized magnetic field acts on the free layer 754 in a direction proceeding from the lower left towards the upper right of the drawing sheet. If the direction of the current flowing through the word line 711 and the bit line 712 is reversed, the direction of the synthesized magnetic field, acting on the free layer 754, is reversed, and proceeds from the upper right side towards the lower left side. This reverses the magnetization of the free layer 754. Thus, data writing may be performed by controlling the direction of the current flowing through the word line 711 and the bit line 712.
Data readout may be realized by measuring the current flowing through the TMR or the voltage across both ends of the TMR to make indirect measurement of the resistance value of the TMR. If the resistance value of the TMR in the ‘0’ storage state is R and that of the TMR in the ‘1’ storage state is (R+ΔR), the MR ratio, defined by MR ratio=ΔR/R×100(%), serves as an index indicating the operating margin of the TMR, and is usually 10 to 30%.
As typical of the MRAM, employing this TMR as a memory cell, a structure in which reference cells are arranged, in addition to the memory cells, in a memory cell array, is disclosed in the U.S. Pat. No. 6,205,073. The resistance value of the reference cell is fixed and is intermediate between the resistance value of the ‘0’ storage state and that of the ‘1’ storage state of the TMR forming the memory cell array. The stored data is read out by converting the current, flowing through the selected memory cell and the reference cell, into the voltage, in an amplifying fashion, and comparing the two voltage values. If the voltage obtained from the memory cell is smaller or larger than the voltage obtained from the reference cell, the storage state of the memory cell is ‘1’ or ‘0’, respectively.
However, the TMR, used as a storage element of the MRAM, is formed by an insulating film of an extremely small thickness and magnetic layers of extremely small thicknesses. It is noted that, for a constant voltage applied, the tunnel current traversing the insulating film, and hence the resistance value of the TMR, are changed exponentially against the thickness thereof. For example, when the thickness of the insulating film becomes thicker or thinner by one atomic layer (2 to 3 Å), the resistance value is varied by 20 to 30%. It is however difficult to generate a uniform insulating film with film thickness variations of the order of an atomic layer. These variations in the resistance value of the TMR become more outstanding as the TMR area is decreased. Thus, the MRAM of the above-described conventional art suffers from the problem that, even though the storage state of the memory cell is ‘1’ or ‘0’, the voltage obtained from the memory cell becomes larger or smaller than the voltage obtained from the reference cell, respectively, thus deteriorating the cell yield.
For overcoming the problem due to the variations in the resistance value of the TMR, there is disclosed in the U.S. Pat. No. 6,188,615 an MRAM in which the recording state may be read out by a self-referencing system, without employing the reference cell. FIG. 23 depicts a block circuit diagram of the MRAM of the prior art, which is composed of a memory cell array 802 and a readout circuit 801. The memory cell array 802 is formed by a matrix of memory cells each formed by a sole TMR 810 present at a point of intersection of a word line 811 and a bit line 812 lying at right angles to each other. During readout, only a cell selected by an X-selector and a Y-selector is connected to the readout circuit 801, such that only the current flowing through the selected cell by the voltage applied across both terminals of the selected cell is entered to the readout circuit 801. The readout circuit 801 is made up by an integrating means 830, a voltage comparator 808A, a counter 805, a preset register 807A, a decision means 808, a reference pulse generating means 834, and a control circuit 809. The integrating means 830 includes a charge amplifier 833 and an integrating capacitor 832.
The current flowing through the selected cell is converted in an amplifying fashion into voltage and integrated. The readout circuit 801 indirectly measures the resistance value of the selected cell by measuring the time Tint until the voltage Vint, integrated by the integrating means 830, becomes equal to the reference voltage Vr. The voltage comparator 808A compares the voltage Vint to the voltage Vr at all times and, by the counter 805 counting the number of reference pulses of a preset period, generated by the reference pulse generating means 834, during the time when Vint≦Vr, the time Tint is converted into a digital value proportionate to the counted number of pulses.
FIG. 24 depicts a view for explaining the operation of a readout circuit of FIG. 23. In a first readout, the number of pulses c1st(0), as counted by the counter 805 when the TMR of the selected cell is in the ‘0’ storage state, is smaller than the number of pulses c1st(1), as counted by a counter 805 when the TMR of the selected cell is in the ‘1’ storage state. This selected cell is then written to the state ‘0’ or ‘1’ and, in the second readout, as in the first readout, the number of pulses c2nd is counted by the counter 805 until Vint=Vr. In FIG. 24, the selected cell is written to the ‘0’ storage state. The storage state of the selected cell for the first readout is determined by the count number of the first and the second readouts.
FIG. 25 depicts a flowchart for illustrating the operation of the readout circuit shown in FIG. 23. When a memory cell is selected (step S801), a count value CNT=d/2 is loaded in the counter 805 (step S802), where d=[c(0)−c(1)]. It is noted that c(0) and c(1) are the count numbers as counted by the counter 805 until the integrated voltage Vint is equal to the reference voltage Vr when the TMR is in the ‘0’ storage state and in the ‘1’ storage state, respectively. These are measured using e.g., an arbitrary memory cell in the memory array. In this case, d assumes a negative value. The first readout is then carried out (step S803). The count value CNT of the counter 805 is equal to the sum of the count value c1st, obtained by the first readout, and d/2. After [−(c1st+d/2)] is stored in the preset register 807A, the contents thereof are re-loaded in the counter 805 (step S804). The ‘0’ storage state is then written in the selected cell (step S805). The second readout is then carried out (step S806). The count value CNT of the counter 805 is equal to the sum of the count value c2nd, obtained by the second readout, and the count value [−(c1st+d/2)] already loaded, that is, [c2nd−(c1st+d/2)]. The decision means 808 then verifies the sign of the CNT (step S807). If the CNT is positive, the storage state for the first readout of the selected cell is determined to be ‘0’ (step S808). The readout operation then comes to a close. If the CNT is negative, the storage state for the first readout of the selected cell is determined to be ‘1’ (step S809). If the storage state of the selected cell is determined to be ‘1’, the ‘1’ storage state is re-written in the selected cell as necessary (step S810) to terminate the readout operation.
By carrying out the readout twice, in this manner, the storage state of a cell in the MRAM may be checked by the self-referencing system, without using reference cells.
In the above-described self-referencing system, in which the difference between the ‘0’ storage state and the ‘1’ storage state of the memory cell itself is used for determining the storage state of the memory cell, it is possible to reduce the effect of the variations in the resistance values from one memory cell to another, In the above-described conventional technique, such a sequence of time-consuming operations consisting in loading d/2, as a constant, in a counter, or in reversing the sign of the count value of the counter after first readout, saving the count value in a preset register and in re-loading the contents in a counter, is required. For avoiding this inconvenience, it is sufficient if a register for storage of the results of the first readout is discretely provided, and the results of the first readout are then stored in this register until the second readout is finished. However, this needs a register circuit for several bits, thus increasing the circuit area. Moreover, an integrating capacitor, provided in the integrating means, also increases the circuit area. For example, if the resistance value of a sole TMR is 100 kΩ, the voltage drop across both terminals of the TMR is 0.5V, the voltage Vr is 0.5V and the integrating time is 1 μsec, the capacitance of 10 pF is needed as the capacitance of the integrating capacitor. For implementing the capacitance of 10 pF in the integrating circuit, an area not less than 40×40 μm2 is needed, with the use of the gate capacitance. In addition, the PLL, routinely used as a reference pulse generating means, also acts for increasing the circuit area or power consumption.